Data di Pubblicazione:
2006
Abstract:
Power efficiency in switched common source class-E
amplifiers is usually obtained at the expense of device stress. Device
stacking is a viable way to reduce voltage drops across a single device,
improving long-term reliability. In this paper,we focus on cascode-
based topologies, analyzing the loss mechanisms and giving
direction to optimize the design. In particular, a new dissipative
mechanism, peculiar of the cascode implementation, is identified
and a circuit solution to minimize its effect is proposed. Prototypes,
realized in a 0.13- m CMOS technology demonstrate 67% PAE
while delivering 23 dBm peak power at 1.7 GHz. Good bandwidth
was also realized with greater than 60% PAE over the frequency
range of 1.4–2 GHz.
amplifiers is usually obtained at the expense of device stress. Device
stacking is a viable way to reduce voltage drops across a single device,
improving long-term reliability. In this paper,we focus on cascode-
based topologies, analyzing the loss mechanisms and giving
direction to optimize the design. In particular, a new dissipative
mechanism, peculiar of the cascode implementation, is identified
and a circuit solution to minimize its effect is proposed. Prototypes,
realized in a 0.13- m CMOS technology demonstrate 67% PAE
while delivering 23 dBm peak power at 1.7 GHz. Good bandwidth
was also realized with greater than 60% PAE over the frequency
range of 1.4–2 GHz.
Tipologia CRIS:
1.1 Articolo in rivista
Keywords:
Power amplifier; transmitters; CMOS
Elenco autori:
Mazzanti, Andrea; Larcher, L.; Brama, R.; Svelto, Francesco
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