A PLL-based frequency synthesizer for 160-MHz double-sampled SC filters

This paper describes a clock generator for a double-sampled switched capacitor (SC) filtering system. The circuit is based on a fast charge-pump phase-locked loop (PLL) system that multiplies an external reference clock signal by a factor of eight and also ensures a high precision and stability of two internal nonoverlapped clock phases up to 80 MHz. This allows the driving of double-sampled SC filters up to 160 MHz sampling rate. The PLL is a third-order system with a bandwidth of 100 kHz and a lock-in time of 15 μs. The output clock jitter is 170 ps r.m.s. The total power consumption at 160 MHz is 25 mW and the total chip area is about 1 mm2