Analysis and Design of a CMOS $E$-Band Frequency Quadrupler With Transformer-Based Harmonic Reflectors

A frequency quadrupler based on cascaded push-push frequency doublers (PPFDs) is presented in this work. PPFDs have high harmonic rejection, but suffer from limited power efficiency and conversion gain, mainly due to second-harmonic feedback. Conventional harmonic reflectors (HRs) minimize this undesired feedback introducing a common-mode second-harmonic resonance, at the price of increased area and reduced bandwidth. In the proposed design, the HR is embedded into a transformer-based input-matching network to decouple the differential-mode inductance from the common-mode inductance. This results in a more compact design, with higher output power and improved power efficiency. A common-gate transistor is stacked with the push-push pair to further boost the output power while reusing the same current. Two PPFDs are cascaded without additional power amplification stages. The quadrupler, implemented in 28-nm CMOS, achieves a peak output power of 0 dBm and peak power efficiency of 5% at 77 GHz and the 3-dB bandwidth is from 70 to 86 GHz.