72-mW CMOS 802.11a direct conversion front-end with 3.5-dB NF and 200-kHz 1/f noise corner

A direct conversion 802.11a receiver front-end including
a synthesizer with quadrature VCO has been integrated in
a 0.13- m CMOS process. The chip has an active area of 1.8 mm2
with the entire RF portion operated from 1.2 V and the low frequency
portion operated from 2.5 V. Its key features are a current
driven passive mixer with a low impedance load that achieves
a low 1 f noise corner and an high I–Q accuracy quadrature
VCO. Measured noise figure is 3.5 dB with an 1 f noise corner
of 200 kHz, and an IIP3 of 2 dBm. The synthesizer DSB phase
noise integrated over a 10 MHz band is less than 36 dBc while
its I–Q phase unbalance is below 1 degree.