A radiation hard bipolar monolithic front-end readout

A fast bipolar monolithic charge sensitive preamplifier (CSP), implemented in the monolithic 2m BiCMOS technology (called HF2CMOS) was designed and built in a quad monolitic chip. Studies of radiation effects in the CSP performance, from non-irradiated and up to neutron irradiation of 5.3x1014n/cm2, have confirmed that the use of bipolar npn transistors is suitable for the radiation level of the future LHC collider environment. The CSP presents a new circuit solution for obtaining adequate slew rate performances which results in an integral linearity better than 0.8% on 5 V at 20 ns of shaping time, regardless of the bias current selected for the CSP. This way the bias current of the CSP can be set for optimizing the power dissipation with respect to series and parallel noise, especially useful when the CSP is put in a radiation environment. A prototype test with a novel monolithic 20 ns time constant RC-CR shaper, capable to sum up four inputs has been also realized, featuring good integral linearity.