Skip to Main Content (Press Enter)

Logo UNIPV
  • ×
  • Home
  • Degrees
  • Courses
  • Jobs
  • People
  • Outputs
  • Organizations

UNIFIND
Logo UNIPV

|

UNIFIND

unipv.it
  • ×
  • Home
  • Degrees
  • Courses
  • Jobs
  • People
  • Outputs
  • Organizations
  1. Outputs

A Novel Repetitive Controller Assisted Phase-Locked Loop with Self-Learning Disturbance Rejection Capability for Three-Phase Grids

Academic Article
Publication Date:
2020
abstract:
The synchronization between the power grid and distributed power sources is a crucial issue in the concept of smart grids. For tracking the real-Time frequency and phase of three-phase grids, phase-locked loop (PLL) technology is commonly used. Many existing PLLs with enhanced disturbance/harmonic rejection capabilities, either fail to maintain fast response or are not adaptive to grid frequency variations or have high computational complexity. This article, therefore, proposes a low computational burden repetitive controller (RC) assisted PLL (RCA-PLL) that is not only effective on harmonic rejection but also has remarkable steady-state performance while maintaining fast dynamic. Moreover, the proposed PLL is adaptive to variable frequency conditions and can self-learn the harmonics to be canceled. The disturbance/harmonic rejection capabilities together with dynamic and steady-state performances of the RCA-PLL have been highlighted in this article. The proposed approach is also experimentally compared to the synchronous rotation frame PLL (SRF-PLL) and the steady-state linear Kalman filter PLL (SSLKF-PLL), considering the effect of harmonics from the grid-connected converters, unbalances, sensor scaling errors, dc offsets, grid frequency variations, and phase jumps. The computational burden of the RCA-PLL is also minimized, achieving an experimental execution time of only 12~mu ext{s}. © 2013 IEEE.
Iris type:
1.1 Articolo in rivista
List of contributors:
Tang, M.; Bifaretti, S.; Pipolo, S.; Odhano, S.; Zanchetta, P.
Authors of the University:
ZANCHETTA PERICLE
Handle:
https://iris.unipv.it/handle/11571/1372695
Full Text:
https://iris.unipv.it//retrieve/handle/11571/1372695/650329/PLL_50Hz_JESTPE_final_final.pdf
Published in:
IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS
Journal
  • Overview

Overview

URL

https://www.scopus.com/inward/record.uri?eid=2-s2.0-85084731744&doi=10.1109/JESTPE.2019.2941835&partnerID=40&md5=e4b121f849bb1b7b6c577e2058137c24
  • Use of cookies

Powered by VIVO | Designed by Cineca | 26.4.0.0