Method for programming nonvolatile memory cells with program and verify algorithm using a staircase voltage with varying step amplitude

Patent
Publication Date:
2001
Iris type:
6.1 Brevetto
Keywords:
NON-VOLATILE MEMORIES; FLASH MEMORIES; MULTILEVEL MEMORIES; MEMORY PROGRAMMING; PROGRAMMING ALGORITHM; STAIRCASE PROGRAMMING
List of contributors:
Handle:
https://iris.unipv.it/handle/11571/151792