Method for programming multi-level non-volatile memories by controlling the gate voltage

Patent

Publication Date:

1999

Iris type:

6.1 Brevetto

Keywords:

NON-VOLATILE MEMORIES; FLASH MEMORIES; MULTILEVEL MEMORIES; MEMORY PROGRAMMING

List of contributors:

Torelli, Guido; A., Modelli; A., Manstretta

Handle:

https://iris.unipv.it/handle/11571/449643