Circuit device for performing hierarchic row decoding in non-volatile memory devices

Patent

Publication Date:

2000

Iris type:

6.1 Brevetto

Keywords:

NON-VOLATILE MEMORIES; FLASH MEMORIES; HIERARCHICAL DECODING

List of contributors:

O., Khouri; A., Pierin; R., Micheloni; Gregori, Stefano; Torelli, Guido; M., Sangalli

Handle:

https://iris.unipv.it/handle/11571/449657