ID:
502515
Duration (hours):
61
CFU:
6
SSD:
ELETTRONICA
Year:
2025
Overview
Date/time interval
Primo Semestre (29/09/2025 - 16/01/2026)
Syllabus
Course Objectives
The goal of the course is to provide the basic knowledge for the design of microelectronic CMOS digital systems, from the elementary devices (complementary CMOS and transmission gate based logic structures) to functional blocks of medium complexity.
Different approaches to integrate a digital system are discussed. The main issues and problems related to the different phases of the design and to the development of a digital circuit are analyzed. Reasons for testing a logic circuit and techniques for design for testability are discussed.
At the end of the course, the student will be familiar with electrical aspects of digital electronics, able to design, from the functional description, the schematic and the layout of simple complementary gates and synchronous circuits.
Different approaches to integrate a digital system are discussed. The main issues and problems related to the different phases of the design and to the development of a digital circuit are analyzed. Reasons for testing a logic circuit and techniques for design for testability are discussed.
At the end of the course, the student will be familiar with electrical aspects of digital electronics, able to design, from the functional description, the schematic and the layout of simple complementary gates and synchronous circuits.
Course Prerequisites
Boole’s Algebra. Analysis and synthesis of digital combinatorial systems, unsigned and two’s complement representation, MOSFET, Inverter CMOS, latch. Knowledge of the basic laws governing electrical circuits
Teaching Methods
Lectures (hours/year in lecture theatre): 30
Practical class (hours/year in lecture theatre): 19
Practicals / Workshops (hours/year in lecture theatre): 12
The lectures are given using slides, power point presentation with explanations and practice at the backboard.
In the laboratory different problems are introduced, followed by practical esperiences with electronic circuits and instruments to consolidate the topics covered in class.
Student reception at the end of the laboratory hours or by appointment (also online)
Practical class (hours/year in lecture theatre): 19
Practicals / Workshops (hours/year in lecture theatre): 12
The lectures are given using slides, power point presentation with explanations and practice at the backboard.
In the laboratory different problems are introduced, followed by practical esperiences with electronic circuits and instruments to consolidate the topics covered in class.
Student reception at the end of the laboratory hours or by appointment (also online)
Assessment Methods
The exam consists of : 1) exercises (time available: 2,5 hours) related with the analysis and/or design of digital systems (weight of 0.6 on the final score). Books and notes are allowed during the test. 2) a brief (30 minutes) written theoretical section where 30 multiple choices tests, problems and theory questions are proposed (weight of 0.4 on the final score). No text (books, notes and so on) will be allowed during the test. the tests must be taken on the same day.
In case of doubt about the originality of the solution proposed by the student, the teacher reserves the right to schedule an oral interview in the days immediately following the written exam for an in-depth discussion of the tests.
In the case of remote exams (only if authorized by the University of Pavia) the second text is replaced by an oral exam, to which the student is admitted only if the written evaluation is higher than 18/30.
The results of the tests are communicated by personal email.
In case of doubt about the originality of the solution proposed by the student, the teacher reserves the right to schedule an oral interview in the days immediately following the written exam for an in-depth discussion of the tests.
In the case of remote exams (only if authorized by the University of Pavia) the second text is replaced by an oral exam, to which the student is admitted only if the written evaluation is higher than 18/30.
The results of the tests are communicated by personal email.
Texts
Copies of the slides used during the lectures,exercises, examples of written tests, instruction manuals and notes provided by the professor for the lab are available from the course website (in italian). Additional material available on Kiro platform.
In order to facilitate the training of students unable to participate in presence, solved exercises and recordings of lessons are available (in Italian).
In order to facilitate the training of students unable to participate in presence, solved exercises and recordings of lessons are available (in Italian).
Contents
Digital Integrated Circuits
CMOS fabrication process, passive components, masks and design rules.
CMOS circuits and basic sequential systems
CMOS gates. Static and dynamic parameters. Transmission gates. Open drain and tri-state outputs. Schmitt trigger inputs. Digital buffers. Layout of a CMOS gate. Level sensitive latch. Edge triggered register. Timing. Registers, binary counters, shift counters.
Adders
Addition, change of sign and subtraction of positive integers and signed integers. Range extension and arithmetic shifts. Full adder, Ripple carry adder.
Digital systems: technology choice
ASIC Standard Cell and Full Custom, Gate Array, Sea of Gates, FPGA.
Testing a digital system
Stuck at, short and open fault, Design For Testability, Built In Self Test, Boundary Scan.
Exercises and Laboratory
Exercises on the course topics are solved directly by the teacher, or proposed as homework with professor review to highlight and correct errors and misunderstanding. Experimental laboratories consist in the realization of simple combinatorial and sequential circuits.
CMOS fabrication process, passive components, masks and design rules.
CMOS circuits and basic sequential systems
CMOS gates. Static and dynamic parameters. Transmission gates. Open drain and tri-state outputs. Schmitt trigger inputs. Digital buffers. Layout of a CMOS gate. Level sensitive latch. Edge triggered register. Timing. Registers, binary counters, shift counters.
Adders
Addition, change of sign and subtraction of positive integers and signed integers. Range extension and arithmetic shifts. Full adder, Ripple carry adder.
Digital systems: technology choice
ASIC Standard Cell and Full Custom, Gate Array, Sea of Gates, FPGA.
Testing a digital system
Stuck at, short and open fault, Design For Testability, Built In Self Test, Boundary Scan.
Exercises and Laboratory
Exercises on the course topics are solved directly by the teacher, or proposed as homework with professor review to highlight and correct errors and misunderstanding. Experimental laboratories consist in the realization of simple combinatorial and sequential circuits.
Course Language
Italian
More information
For students of categories recognized by the University as having the right to compensatory measures, or who, for reasons recognized by the University, cannot attend the course in presence, appropriate teaching methods are applied, including the availability recorded lessons. Additional Office hours will be offered, even remotely.
Degrees
Degrees (2)
ELECTRONIC AND COMPUTER ENGINEERING
Bachelor’s Degree
3 years
COMPUTER ENGINEERING
Master’s Degree
2 years
No Results Found